Deep neural networks (“DNNs”) are loosely modeled after information processing and communication patterns in biological nervous systems, such as the human brain. DNNs can be utilized to solve complex classification problems such as, but not limited to, object detection, semantic labeling, and feature extraction. As a result, DNNs form the foundation for many artificial intelligence (“AI”) applications, such as computer vision, speech recognition, and machine translation. DNNs can match or exceed human accuracy in many of these domains.
The high-level of performance of DNNs stems from their ability to extract high-level features from input data after using statistical learning over a large data set to obtain an effective representation of an input space. However, the superior performance of DNNs comes at the cost of high computational complexity. High performance general-purpose processors, such as graphics processing units (“GPUs”), are commonly utilized to provide the high level of computational performance required by many DNN applications.
While general-purpose processors, like GPUs, can provide a high level of computational performance for implementing DNNs, these types of processors are typically unsuitable for use in performing DNN operations over long durations in computing devices where low power consumption is critical. For example, general-purpose processors, such as GPUs, can be unsuitable for use in performing long-running DNN tasks in battery-powered portable devices, like smartphones or alternate/virtual reality (“AR/VR”) devices, where the reduced power consumption is required to extend battery life.
Reduced power consumption while performing continuous DNN tasks, such as detection of human movement, can also be in non-battery powered devices, such as a power-over-Ethernet (“POE”) security camera for example In this specific example, POE switches can provide only a limited amount of power, and reduced power in POE devices like security cameras results in lower power consumption and cost of POE switches.
Application-specific integrated circuits (“ASICs”) have been developed that can provide performant DNN processing while at the same time reducing power consumption as compared to general-purpose processors. Despite advances in this area, however, there is a continued need to improve the performance and reduce the power consumption of ASICs that perform DNN processing, particularly for use in computing devices where the low power consumption is critical.
Current practices provide for various mechanisms to manage memory and/or processing to ensure a balance between requesting components for shared resources of an exemplary computing environment. With current practices, such memory/processor management falls short to optimize the overall utility of each of the available processing elements such as neurons of a cooperating DNN chip. Moreover, current practices focus on overall processing/memory management of the system without possible regard to the overall power consumption and processing performance of the DNN chip.
It is with respect to these and other technical challenges that the disclosure made herein is presented.